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Semiconductor Architecture

All digests tagged Semiconductor Architecture

The Inference Frontier: from 100 to 10,000 tokens per second — Sean Lie, Cerebras CTO thumbnail

· 44:03

The Inference Frontier: from 100 to 10,000 tokens per second — Sean Lie, Cerebras CTO

Cerebras CTO Sean Lie details the shift in AI infrastructure from merely increasing model size to achieving ultra-fast inference speeds. The core argument is that speed (throughput) itself enables entirely new classes of intelligent applications and agents. Cerebras showcased its CS4 wafer-scale architecture, demonstrating GPTOSS running at over 4,400 tokens per second (TPS). They previewed the next generation, CS5, which aims for up to 10,000 TPS on medium models and 5,000 TPS on frontier models. The industry is moving toward heterogeneous, disaggregated systems that integrate specialized components like OpenAI's Jalapeño chip to solve complex scaling challenges.

Key takeaways

  1. Speed Defines Capability 0:35

    What was once considered fast (100–200 TPS) is now viewed as 'batch mode.' Ultra-fast inference enables more reasoning loops and significantly more capable agents, transforming previously offline applications into real-time experiences.

  2. CS4 Performance Milestone 3:05

    The CS4 architecture is a modular platform designed to bring wafer scale to hyperscale. It provides significantly more power and interconnect bandwidth, demonstrated by running GPTOSS at over 4,400 TPS.

  3. CS5 Roadmap (Preview) 7:56

    The next generation CS5 platform is designed for multiple generations of products. It aims to push performance further: up to 10,000 TPS for medium models (e.g., Gemma) and up to 5,000 TPS for frontier models (e.g., Gemini/DeepSeek).

  4. The Future is Heterogeneous & Disaggregated 11:20

    Lie argues that the future of AI infrastructure requires integrating specialized components—such as prefill, attention, and KV cache loading—across different hardware types (e.g., wafer scale, SRAM-based chips like Jalapeño) to solve scaling challenges.

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IBM’s mainframe chip collab, NVIDIA’s Poolside deal & Ox Alpha’s reveal thumbnail

· 30:59

IBM’s mainframe chip collab, NVIDIA’s Poolside deal & Ox Alpha’s reveal

The discussion covered major developments in AI infrastructure, focusing on IBM's new dual-architecture mainframe processor combining z/OS and Arm. This aims to bring modern AI workloads closer to mission-critical data residing on mainframes. Furthermore, NVIDIA's strategy was analyzed through its $6 billion deal with Poolside and the acquisition of Hugging Face, positioning NVIDIA as a central player in the open-source AI ecosystem by controlling key software standards. Finally, the reveal of Z.ai’s GLM-5.3-Flash model highlighted the trend toward stealth model releases.

Key takeaways

  1. IBM's Dual-Architecture Mainframe Processor 21:50

    IBM unveiled a new dual processor architecture at Hot Chips that combines IBM Z (mainframe workload) with Arm. This allows systems to run Arm-native Linux workloads alongside z/OS, addressing the challenge of integrating modern AI software into mission-critical mainframe environments.

  2. NVIDIA's Open Ecosystem Strategy 2:00

    NVIDIA is making a strategic play to be the center of open-source AI by acquiring Hugging Face (the cornerstone of open AI software) and securing a $6 billion license deal with Poolside. This solidifies their position in hardware while maintaining an open model ecosystem.

  3. LLM Model Release Tactics 24:30

    The anonymous 'Ox Alpha' model was revealed to be Z.ai’s GLM-5.3-Flash, an open-source LLM built with sparse and linear attention techniques. The discussion noted that stealth launches are a highly effective marketing strategy for generating hype and speculation.

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