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All digests tagged GPU Architecture
Learn how progressive IR lowering transforms PyTorch layers into efficient GPU kernels. We explore the compiler stack: PyTorch $\rightarrow$ Tensor AR $\rightarrow$ Loop IR $\rightarrow$ Tile IR $\rightarrow$ CUDA, detailing fusion, normalization, and tiling for maximum performance.
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Learn how ML compilers progressively lower PyTorch graphs to efficient CUDA kernels. We explore the IR stack: from PyTorch to Loop IR, Tiling, and Kernel IR, detailing fusion and scheduling.
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The biggest AI models require distributed inference because they exceed single GPU memory capacity. Learn how Data, Pipeline, Tensor, and Expert parallelism scale LLMs across multiple GPUs.
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Learn how NVFP4 compares to BF16 for Nemotron 3.5 Lightning. Discover how this low-precision format shrinks memory footprint and boosts inference speed without a major quality hit.
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Mega kernels fuse entire forward passes into one persistent kernel, eliminating traditional GPU overheads like global synchronization and SRAM clearing. This enables fine-grained scheduling by allowing cores to dynamically pick up slack from slower units.
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